1. Field of the Invention
This invention relates to a high potential hold circuit, the purpose of which is to hold the high potential at the drain (or source) side of MOS transistor. The MOS transistor is set in its non-conducting state by maintaining the gate potential at reference ground potential.
2. Description of the Prior Art
Conventionally, this type of high potential hold circuit is used as a signal delay circuit employed in dynamic RAM circuits. FIG. 1 shows a circuit diagram of a signal delay circuit. MOS transistor Q1, the conduction of which is controlled by input signal .phi.in, and MOS transistor Q2, the conduction of which is controlled by clock signal .phi., are connected in series between power supply Vdd and ground Vss.
The gate of MOS transistor Q3, one end of which is connected to ground supply Vss, is connected to the junction (node N1) formed between MOS transistors Q1 and Q2. MOS transistor Q4, the conduction of which is controlled by clock signal .phi., is connected between the other end of MOS transistor Q3 and power supply Vdd. The gate of MOS transistors Q6 and Q7, each of which have one end thereof connected to ground Vss, are respectively connected to the junction (node N2) formed between MOS transistors Q3 and Q4, and one end of MOS transistor Q5, the gate of which is applied to power supply voltage Vdd. The gate of MOS transistor Q8, one end thereof which receives input signal .phi.in, is connected to the other end (node N3) of MOS transistor Q5. MOS transistor Q9, the conduction of which is controlled by clock signal .phi.', is connected between the other end of MOS transistor Q8 and ground Vss. The gate of MOS transistor Q11, which is connected between the other end of MOS transistor Q7 and power supply Vdd, is connected to the junction (node N4) formed between MOS transistor Q8 and Q9, and the gate of MOS transistor Q10, one end thereof which is connected to power supply Vdd, and the other, to node N5, which is other end of MOS transistor Q6. An enhancement mode MOS capacitor C1 is connected across the gate and drain of MOS transistor Q10, between node N4 and N5. The aforementioned output signal .phi.out, which is delayed, is obtained from the junction formed between MOS transistors Q11 and Q7. The following explanation is an operational description of the circuit configuration described above.
With clock signals .phi. and .phi.', in their high (`H`) level state, the potentials at N2 and N3 are changed to (vdd Vth) (where Vth represents the threshold voltage of the MOS transistor, which for the purpose of simplifying the explanation can be regarded as being equal for all the MOS transistors). This being the case, nodes, N1, N4 and N5, input signal .phi.in, and output signal .phi.out are at ground potential Vss.
Then, when input signal .phi.in increases from ground, with clock signals .phi. and .phi.' in their low (`L`) level states, the potential at node N2 becomes equal to (Vdd-Vth), and MOS transistor Q5 ceases to conduct. As a result of the increase in input signal .phi.in, potential V3 of node N3 rises due to the capacitive coupling between the gate and drain of MOS transistor Q8. Consequently, MOS transistor Q8 is able to operate in the triode region, and potential V4 of node N4 becomes equal to input signal .phi.in. When potential V4 exceeds threshold voltage Vth of MOS transistor Q10, MOS transistor Q10 conducts and node N5 starts to charge. At this point, the potential at node N2 drops due to the conduction of MOS transistor Q3. MOS transistor Q6 ceases to conduct, and the charge supplied from power supply Vdd, through MOS transistor Q10, is `latched in` by node N5.
As a result, the increase in potential V4 at node N4 is accelerated due to the capacitive coupling of MOS capacitor C1. The moment potential V4 exceeds power supply voltage Vdd, potential V3 becomes equal to ground potential Vss, due to the conduction of MOS transistors Q3 and Q5. Since MOS transistor Q8 is in a non-conducting state, the charge accumulated at node N4 is held at high potential, without being able to escape.
At this point, the delayed signal .phi.out of input signal .phi.in, which has suffered no losses due to the threshold voltage Vth, is obtained, as a result of MOS transistor Q11 operating in its triode region.
This condition may be reset by setting input signal .phi.in to its low `L` level state, and clock signals .phi. and .phi.' to their high `H` level states. However, in order to obtain output signal .phi.out, by correctly delaying the input signal .phi.in, potential V4 at the gate of MOS transistor Q11 is increased beyond (Vdd+Vth), thus making it necessary to maintain this condition. In the aforementioned circuit shown in FIG. 1, the charge at node N4 is supplied via MOS transistor Q8, which is then placed in its non-conducting state, thus holding the potential at node N4. Thus, the gate potentials of MOS transistors Q8 and Q9 are pulled to ground potential Vss, as was usually the case in the past when holding high potentials. In this state, however, the electric field between the gate and drain (or source) being quite strong, with the addition of the electric field between the drain and source, gives rise to surface breakdown. The repeated application of strong electric fields, if only for short periods at a time, results in a loss of circuit reliability due to the very low breakdown voltage as a result of the extremely thin dioxide layer between the gate and drain (or source) of the transistor.
Also, the promotion of miniaturised micro-circuit technology necessitated the introduction of further reductions to drain-source geometries making the device all the more susceptible to punch through. This made the achievement of lower source-drain voltages even more desirable.
The circuit shown in FIG. 2 is proposed as a signal delay circuit capable of eliminating this particular drawback. In this circuit, MOS transistor Q12, the conduction of which is established by power supply voltage Vdd, is inserted between high potential node N4 and MOS transistor Q9. An abbreviated explanation of this circuit is given with reference to FIG. 2, by inclusion of symbols similar to those applied to the same component parts in FIG. 1.
In this configuration, the potential at the junction (node N6) formed between MOS transistors Q9 and Q12 is (Vdd-Vth) (where Vth is the threshold of MOS transistor Q12), even though the potential V4 at node N4 is very high. The potential difference between the gate and drain (or source) of MOS transistor Q9 relaxes from (Vdd+Vth) to (Vdd-Vth), that is, by more than 2 Vth, in the circuit of aforementioned FIG. 2, thus making it possible to improve the device breakdown voltage and circuit reliability.
Also, since the potential difference between the source and drain of MOS transistor Q9 could be reduced, punch through countermeasures were also improved. However, a MOS transistor, capable of being turned on by power supply voltage Vdd, could not be provided between MOS transistor Q8 and node N4, as was the case in aforementioned MOS transistor Q12. Because, by inserting a MOS transistor between MOS transistor Q8 and node N4, the potential at node N4 would drop by about value of threshold voltage Vth. The accompanying delay to the increase in potential at node N4 would then bring about a reduction to the final potential.
Consequently, when input signal .phi.in, when active, drops to ground potential Vss, MOS transistor Q8 suffers the same unresolvable drawback as MOS transistor Q9, notwithstanding the questionable reliability similar to that of MOS transistor Q9.